The safety infrastructure landscape — who builds what

When you look at the safety infrastructure landscape for Physical AI, the first thing you notice is how much already exists. The building blocks are there. The harder question has always been the integration layer that ties them together — and in June 2026 that question got a very big new answer.

Start with standards bodies. The IEC published IEC 61508 — the parent standard for functional safety — in 1998, with a major revision in 2010. ISO published 13849 for machinery safety and 26262 for automotive. IEEE has working groups on autonomous systems safety. UL published UL 3115 for AI safety certification in October 2025. The standards exist.

Certification houses have been assessing safety-critical systems for decades. TÜV SÜD, TÜV Rheinland, and TÜV Nord collectively certify systems across automotive, industrial, medical, and rail. Pilz specializes in machinery safety. UL and Intertek cover global markets. The certification infrastructure exists.

Safety silicon exists. Infineon's AURIX family is the dominant automotive safety microcontroller, designed and certified to IEC 61508 SIL 3 and ISO 26262 ASIL D. Renesas offers the RH850 family for functional safety applications. Texas Instruments builds the Hercules safety MCU line. Microchip provides certified safety controllers. The hardware building blocks for safety-critical computation exist and are in mass production.

Safety PLCs exist. Siemens, Pilz, Allen-Bradley (Rockwell), SICK, and HIMA all manufacture programmable logic controllers specifically designed and certified for safety-critical applications. These are the workhorses of industrial functional safety — the devices that implement safe shutdown sequences, monitor interlocks, and execute safety functions in process plants, manufacturing lines, and energy systems.

AI safety certification matured fast. NVIDIA first launched Halos certification for physical AI in 2025; on 22 June 2026 it went much further, announcing Halos for Robotics — described as the industry's first full-stack safety system for physical AI, pairing safety-capable compute (an independent on-chip safety processor) with a safety software stack and an accredited inspection lab. More than 40 partners signed on, and Agility's humanoid Digit is the first adopter. UL 3115 provides a complementary certification framework. The signal is unambiguous: the industry now treats AI-specific hardware safety as a product category, not a research topic.

For two years, one lane on this map was empty: the layer that sits between the AI decision-making system and all of these existing safety components — for robots specifically. As of 22 June 2026, that lane has its first major occupant. The gap has not closed, though — it has moved.

What is still missing is a vendor-neutral, independent version of that layer. NVIDIA's safety processor is a real step forward, but it lives on the same chip, from the same vendor, designed by the same team as the AI compute it supervises. Functional safety's entire history — aviation, nuclear, rail — says the highest integrity levels require independence and diversity from the system being judged, not just isolation inside it. The open lane now is a safety layer that works across robot platforms that do not run on a single vendor's stack, and that can serve as a genuinely diverse second channel for the ones that do. No such product category exists yet, and no plug-and-play, vendor-independent certification path lets an arbitrary robot OEM connect any AI system to the existing safety infrastructure in a way that a certification body can assess.

The building blocks exist. As of June 2026, the first full-stack integration layer exists too — tied to one vendor. The independent, cross-platform version is the gap that's left on the map.